Recogni unveils Pareto, a breakthrough in AI chip efficiency

Recogni has announced a new logarithmic number system, named Pareto, which promises significant improvements in power efficiency, computational speed, and chip size for generative artificial intelligence (AI) applications. The company claims that Pareto addresses key challenges in AI chip design without compromising accuracy.

The Pareto logarithmic system aims to transform multiplications into additions, a method that reduces power usage and execution time. According to Recogni, this significant change enables their chips to be smaller, faster, and more energy-efficient.

Marc Bolitho, CEO of Recogni, stated, "With Pareto, we accelerate the world's AI ambitions. Pareto's logarithmic number system has the lowest average error and highest performance for AI models. By turning multiplications into additions, Pareto significantly reduces power consumption, latency, and chip size, making it the optimal choice for modern AI chip design." He emphasised that organisations running generative AI inference can keep operational costs lower and maintain high AI model quality with Pareto.

The development of Pareto has spanned seven years, during which Recogni conducted extensive testing on various AI models. These include Mixtral-8x22B, Llama3-70B, Falcon-180B, Stable Diffusion XL, and Llama3.1-405B. The tests showed that Pareto achieved a relative accuracy of over 99.9% compared to the trained high-precision baseline model while consuming significantly less power. This high precision was attained with less than 0.1% drop in accuracy using 16-bit precision and less than 1% using 8-bit precision, eliminating the need for retraining.

Gilles Backhus, founder and VP of AI at Recogni, commented on the benefits of Pareto for developers. "Our goal is and has always been to directly address both the needs of businesses and machine learning developers. With Pareto, we came up with a number system that allows businesses to instantly deploy their models at high power efficiency with virtually no loss across all key performance and accuracy metrics. While companies using standard math are spending considerable time converting models to lower precision to reduce the power and operational expenses, Pareto allows companies to bring new models to production faster and cheaper while maintaining high accuracy."

The new number system outperforms other quantized number systems for generative AI inference by addressing the increased computational demands of modern AI models, which require vast quantities of multiplications and additions, usually measured in petaFLOPS. Pareto's efficiency allows for a compact chip design which results in significant space and cost savings in data centres.

Recogni's initial Pareto chip, developed using a 7nm TSMC process, has already been proven to exceed performance expectations. The company plans to announce a technology partnership that will make Pareto more widely available in the coming months.

Recogni is set to present a detailed exploration of Pareto at NeurIPS 2024. With seven years of research culminating in this advanced logarithmic number system, the company believes Pareto represents a significant step forward in the quest for more efficient and powerful AI computing.